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Intel Customizable Wireless Architecture: Supporting Anything and Anything!
At the Software-Defined Radio Forum that wrapped up this week, Intel revealed some details of its custom wireless architecture.
Intel was preparing a custom RF architecture for the first time at the Intel Developer Forum last year from a speech by Patrick Gelsinger. In developing its architecture, Intel went its own way: instead of using programmable logic (FPGA), the company is going to fill its chip with a heterogeneous array of processors.
The array’s heterogeneity lies in the fact that it will have two main types of processors: general-purpose digital signal processors (DSPs) and processors optimized for processing special algorithms. According to one of the architects Jeffrey Schiffer (Jeffrey Schiffer), the finished chip in its complexity will be something in between FPGA and not too powerful PC processor.
It is also interesting that the processors do not have a common bus, but are connected to a network (more precisely, in a mesh), framed on both sides by an array of input / output (I / O) ports. Intel believes that this architecture will solve the problem of mobile devices that need to stay connected not only when moving from one cell to another, but also from one protocol to another, from one frequency range to another. It is conceived so that a mobile device manufactured according to Intel architecture will constantly poll the network (or networks) for what services are available at a given point (not only space, but also time), and based on the assessment of the situation, configure the processor array in the required PHY / MAC controller (physical layer controller / media access controller).
Of course, this architecture has its drawbacks, and Intel does not hide them. First, the efficiency (in terms of size and power consumption) of such arrays will be worse than that of one or two PHY / MAC controllers located on a single chip. But when the number of required PHY / MAC controllers reaches three, the efficiency of the array is comparable to the efficiency of such a chip. When the number of PHY / MAC controllers on a chip exceeds three, the efficiency of the chip becomes noticeably worse.